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PCI EXPRESSTM JITTER ATTENUATOR
ICS874005-04
GENERAL DESCRIPTION
The ICS874005-04 is a high performance DiffIC S erential-to-LVDS Jitter Attenuator designed for use HiPerClockSTM in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874005-04 has 2 PLL bandwidth modes: 300kHz and 2MHz. The 300kHz mode will provide maximum jitter attenuation, but higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 2MHz bandwidth provides the best tracking skew and will pass most spread profiles. The ICS874005-04 supports Serdes reference clock frequencies of 100MHz, 125MHz and 250MHz. The ICS874005-04 uses IDT's 3 Generation FemtoClock PLL technology to achive the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards.
rd TM
FEATURES
* Five differential LVDS output pairs * One differential clock input * Supports 100MHz, 125MHz, and 250MHz Serdes reference clocks * CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency range: 98MHz - 320MHz * Input frequency range: 98MHz - 128MHz * PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant * RMS phase jitter @ 100MHz (1.875MHz - 20MHz): 0.88ps (typical) * VCO range: 490MHz - 640MHz * Cycle-to-cycle jitter: 35ps (maximum) QA = QB = /4 * 3.3V operating supply * Two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs * 0C to 70C ambient operating temperature * Available in lead-free (RoHS 6) package
PLL BANDWIDTH
BW_SEL 0 = PLL Bandwidth: ~300kHz (default) 1 = PLL Bandwidth: ~2MHz
BLOCK DIAGRAM
OEA Pullup F_SELA Pulldown BW_SEL Pulldown 0 = ~300kHz 1 = ~2MHz CLK Pulldown nCLK Pullup
F_SELA 0 /5 (default) 1 /4
QA0 nQA0 QA1
PIN ASSIGNMENT
nQB2 nQA1 QA1 VDDO QA0 nQA0 MR BW_SEL VDDA F_SELA VDD OEA 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 QB2 VDDO QB1 nQB1 QB0 nQB0 F_SELB OEB GND GND nCLK CLK
Phase Detector
VCO
490 - 640MHz
nQA1 QB0
F_SELB 0 /2 (default) 1 /4
nQB0 QB1 nQB1 QB2 nQB2
M = /5 (fixed)
ICS874005-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm package body
F_SELB Pulldown MR Pulldown OEB Pullup
G Package Top View
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TABLE 1. PIN DESCRIPTIONS
Number 1, 24 2, 3 4, 23 5, 6 7 8 9 10 11 12 13 14 15, 16 17 18 19, 20 21, 22 Name nQB2, QB2 nQA1, QA1 VDDO QA0, nQA0 MR BW_SEL VDDA F_SELA VDD OE A CLK nCLK GND OEB F_SELB nQB0, QB0 nQB1, QB1 Type Output Output Power Output Input Input Power Input Power Input Input Input Power Input Input Output Output Description Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Output supply pins. Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low and the inver ted outputs Pulldown (nQx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pulldown PLL bandwidth input. See Table 3B. LVCMOS/LVTTL interface levels. Analog supply pin. Frequency select pin for QAx/nQAx outputs. See Table 3C. Pulldown LVCMOS/LVTTL interface levels. Core supply pin. Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are active. When LOW, the QAx/nQAx outputs are in a high impedance Pullup state. LVCMOS/LVTTL interface levels. See Table 3A. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Power supply ground. Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are active. When LOW, the QBx/nQBx outputs are in a high impedance Pullup state. LVCMOS/LVTTL interface levels. See Table 3A. Frequency select pin for QBx/nQBx outputs. See Table 3C. Pulldown LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Inputs OEA/OEB 0 1 QAx/nQAx High Impedance Enabled Outputs QBx/nQBx High Impedance Enabled
TABLE 3B. PLL BANDWIDTH CONTROL, fREF = 100MHZ
Inputs BW_SEL 0 1 PLL Bandwidth ~300kHz (default) ~2MHz
TABLE 3C. OUTPUT FREQUENCY FOR INPUT FREQUENCY = 100MHZ
Inputs F_SELA 0 (default) 0 1 1 F_SELB 0 (default) 1 0 1 QAx/nQAx VCO/5, 100MHz VCO/5, 100MHz VCO/4, 125MHz VCO/4, 125MHz Outputs QBx/nQBx VCO/2, 250MHz VCO/4, 125MHz VCO/2, 250MHz VCO/4, 125MHz
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 82.3C/W (0 mps) Storage Temperature, TSTG -65C to 150C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.10 3.135 Typical 3. 3 3.3 3.3 Maximum 3.465 VDD 3.465 80 10 75 Units V V V mA mA mA
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TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = VIN = 3.465V -5 -150 0.15 GND + 0.5 1. 3 VDD - 0.85 Minimum Typical Maximum 15 0 5 Units A A A A V V
Peak-to-Peak Input Voltage; NOTE 1
VCMR Common Mode Input Voltage; NOTE 1, 2 NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.125 1.25 Test Conditions Minimum 247 Typical Maximum 454 50 1.375 50 Units mV mV V mV
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Cycle-to-Cycle Jitter, NOTE 2 Output Skew; NOTE 3 Bank Skew: NOTE 4 Output Rise/Fall Time QAx QBx 20% to 80% 30 0 Test Conditions 100MHz, Integration Range: (1.875MHz - 20MHz) QA, QB = /4 QA = /5 Minimum 98 0.88 35 75 90 15 68 500 Typical Maximum 320 Units MHz ps ps ps ps ps ps ps
tjit() tjit(cc) tsk(o) tsk(b)
tR / tF
odc Output Duty Cycle 48 52 % NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and frequency, and with equal load conditions. Measured at the differential cross points. NOTE 4: Defined as skew within a bank of outputs at the same supply voltage and frequency, and with equal load conditions.
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PARAMETER MEASUREMENT INFORMATION
VDD
SCOPE
3.3V5% POWER SUPPLY + Float GND -
VDD, VDDO
Qx
nCLK
V
PP
VDDA
LVDS
nQx
Cross Points
V
CMR
CLK
GND
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQA0, nQA1 nQB0:nQB2 QA0, QA1 QB0:QB2
tcycle n
nQx Qx
tjit(cc) = tcycle n - tcycle n+1 1000 Cycles
CYCLE-TO-CYCLE JITTER
nQx Qx nQy Qy
tsk(b)
BANK SKEW
IDT TM / ICSTM PCI EXPRESSTM JITTER ATTENUATOR
tcycle n+1
nQy Qy
tsk(o)
OUTPUT SKEW
nQA0, nQA1 nQB0:nQB2 QA0, QA1 QB0:QB2
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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PARAMETER MEASUREMENT INFORMATION, CONTINUED
VDD
VDD out
out
DC Input
LVDS
DC Input
LVDS
out
100
VOD/ VOD out
VOS/ VOS
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
nQA0, nQA1 nQB0:nQB2
80%
QA0, QA1 QB0:QB2
80% VOD
20% tR tF
20%
OUTPUT RISE/FALL TIME
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APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor mance, pow er supply isolation is required. The ICS874005-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD , V DDA and V DDO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS:
LVDS OUTPUTS All unused LVDS output pairs can be either left floating or ter minated with 100 across. If they are left floating, we recommend that there is no trace attached.
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL and LVHSTL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL HiPerClockS Input R1 50 R2 50 Zo = 50 Ohm nCLK HiPerClockS Input CLK
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
2.5V
3.3V
2.5V
2.5V 3.3V
*R3
33
Zo = 50
Zo = 60
R3 120
R4 120
CLK Zo = 50 nCLK
CLK Zo = 60 nCLK
HCSL
*R4
33 R1 50 R2 50
HiPerClockS Input
SSTL
R1 120 R2 120
HiPerClockS
*Optional - R3 and R4 can be 0
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER
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LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS output buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V LVDS_Driv er + R1 100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS874005-04 application schematic. In this example, the device is operated at VDD= 3.3V.
VDD = 3.3V
The decoupling capacitor should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver.
VDDO = 3.3V
Zo = 50 Ohm
+ U1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Zo = 50 Ohm R2 100 nQB2 nQA1 QA1 VDDO QA0 nQAO MR BW_SEL VDDA F_SELA VDD OEA QB2 VDDO QB1 nQB1 QB0 nQB0 F_SELB OEB GND GND nCLK CLK
R1 10
C3 10uF
C4 0.01u
MR BW_SEL F_SELA OEA
F_SELB OEB
Zo = 50 Ohm
+ 874005_tssop24 ICS874005-04 Zo = 50 Ohm nCLK Zo = 50 Ohm R3 100 -
Zo = 50 Ohm CLK
LVPECL Driv er
R4 50 (U1:23) R6 50
R5 50
(U1:11)
(U1:4)
C5 10uf
C6 .1uf
C7 .1uf
C8 .1uf
FIGURE 5. ICS874005-04 SCHEMATIC EXAMPLE
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS874005-04. Equations and example calculations are also provided.
1. Power Dissipation (typical).
The total power dissipation for the ICS874005-04 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
* *
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (80mA + 10mA) = 311.85mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 75mA = 259.875mW
Total Power_MAX = 311.85mW + 259.875mW = 571.725mW
2. Junction Temperature (typical).
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 82.3C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.572W * 82.3C/W = 117.1C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board.
TABLE 6. THERMAL RESISTANCE JA FOR 24-LEAD TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 82.3C/W
1
78.0C/W
2.5
75.9C/W
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RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 82.3C/W
1
78.0C/W
2.5
75.9C/W
TRANSISTOR COUNT
The transistor count for ICS874005-04 is: 1428
PACKAGE OUTLINE AND PACKAGE DIMENSIONS
PACKAGE OUTLINE - G SUFFIX
FOR
24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
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TABLE 9. ORDERING INFORMATION
Part/Order Number 874005AG-04LF 874005AG-04LFT Marking ICS874005A04L ICS874005A04L Package 24 Lead "Lead-Free" TSSOP 24 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel Temperature 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS complaint.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA)
(c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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